1. Field of the Invention
The present invention relates to a power-on reset circuit set in a semiconductor integrated circuit and generating a one-shot power-on reset pulse (one-shot pulse) in the power application to reset other circuits in the semiconductor integrated circuit.
2. Related Art
A conventional power-on reset circuit has a capacitor charge time constant circuit configured by a charge capacitor, and resistance or current generator, and generates a one-shot pulse in the power application. However, there is a problem in the power-on reset circuit having only the capacitor charge time constant circuit that the one-shot pulse is not generated when the ramp-up speed of a power supply voltage is slower than that of capacitor charge time constant. There are descriptions of arts. coping with this problem such as the ones disclosed in the following documents.
Document 1: JP, 63-246919, A
Document 2: JP, 4-72912, A
Document 3: JP, 6-196989, A
Document 4: U.S. Pat. No. 5,930,129
The power-on reset circuit disclosed in the document 1 comprises a flip-flop set in response to a power supply voltage application and a power supply voltage detection circuit resetting the flip-flop forcibly after a prescribed delay from the time of the power supply voltage rising over a prescribed potential.
The power-on reset circuit disclosed in the document 2 comprises a power supply voltage detection circuit detecting the rise of power supply voltage to a prescribed voltage, a delay circuit delaying the output signal of the power supply voltage detection circuit and a waveform shaping circuit achieving a waveform shaping of the output signal of the delay circuit.
The power-on reset circuit disclosed in the document 3 comprises a voltage control means outputting the output voltage, at which the power supply voltage is set, in the output voltage less than a predetermined voltage and a pulse output circuit outputting a prescribed pulse in response to the difference between the input voltage of the voltage control means and a predetermined voltage reaching a prescribed value after inputting the output voltage of the voltage control means.
The power-on reset circuit disclosed in the document 4 comprises: a voltage sensing means; an electric current path disconnecting means; a capacitor charge time constant circuit having a power supply voltage sensing circuit sensing the power supply voltage application when the electric current disconnecting means is turned on, an electric current flowing path means flowing path based on the sensed voltage, a capacitor charging based on the time constant through the electric current flowing path means, and a discharging means; and an output circuit.
However, when the conventional power-on reset circuit is configured by using a minute MOS element in which the off-leakage current through the MOS (under high temperature) tends to increase with recent development of process-minuteness of the semiconductor integrated circuit, there are following problems therein. FIGS. 24-27 are circuit diagrams showing examples of the conventional power-on reset circuit, and are respectively shown in the documents 1-4.
The power-on reset circuit disclosed in the document 1 comprises a flip-flop 2 configured by two inverters 2a and 2b and detecting and keeping the rise of power supply voltage, a capacitor 3 connected to the flip-flop 2, a MOS transistor 4 and a power supply voltage circuit 10. The power supply voltage circuit 10 has two steps of inverters 11 and 12, a MOS diode array 14 configured by plural MOS diodes 13, a capacitor 15 and a MOS transistor 16, the connection of which is shown in FIG. 24.
As described above, the power-on reset circuit disclosed in the document 1 has the configuration that a reset signal for the flip-flop 2 is forcibly generated by establishing a supportive circuit in parallel to a general power-on reset circuit comprising a capacitor, a resistance (MOS diode array) and an inverter. When the off-leakage current is sent on the MOS diode array in the circuit configuration, the charge of the capacitor 15 is started by the off-leakage current through the MOS diode array and a forcible reset signal for the flip-flop 2 is generated at the moment of the power application, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the threshold voltage at the MOS diode array. As a result, a one-shot pulse (power-on reset signal) cannot be accurately generated.
The power-on reset circuit disclosed in the document 2 is configured by a power supply voltage detection circuit 20, a delay circuit 30 and a waveform shaping circuit 40 as shown in FIG. 25. The power supply voltage detection circuit 20 has a resistance 21 and an N-channel type MOS diode 22 which are connected between a power supply potential Vcc and a ground, and has a resistance 24 one end of which is connected to a connection point N1 of the resistance 21 and the MOS diode 22. An inverter 25 operating with the power supply voltage and the drain of an N-channel type MOS transistor (hereafter, referred to as NMOS) 26 are connected to a connection point N2 of resistances 23 and 24. The inverter 25 is configured by a P-channel type MOS transistor (hereafter, referred to as PMOS) 25a and NMOS 25b. The gate of the NMOS 26 is connected to the output terminal of the inverter 25 while the source of the NMOS 26 is connected to the ground. The delay circuit 30 has NMOS 31 the source of which is connected to the output terminal of the inverter 25 and the gate of which is connected to the power supply potential Vcc, and has a capacitor 32 connected between the drain of the NMOS 31 and the ground. The waveform shaping circuit 40 has an inverter 41 the input terminal of which is connected to a connection point N3 of the NMOS 31 and the capacitor 32, and has PMOS 42 the gate of which is connected to the output terminal of the inverter 41.
As described above, the power-on reset circuit disclosed in the document 2 has the configuration that the resistances 21, 23 and 24 in the power supply voltage detection circuit 20 divide the voltage between the power supply potential Vcc and the ground. Therefore, there is a problem that since current flows through the resistances 21, 23 and 24, the current consumption cannot reach 0 even after an one-shot pulse is generated.
Further, when the off-leakage current is sent on the PMOS 42 in the waveform shaping circuit 40 the charge of the capacitor 32 is started by the off-leakage current through the PMOS 42 and the PMOS 42 is forced to be turned on by inverting the output of the inverter 41 and NMOS 26 in the power supply voltage detection circuit 20 is also forced to be turned on, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the prescribed power supply voltage detected at the power supply voltage detection circuit 20. As a result, the one-shot pulse (power-on reset signal) cannot be accurately generated.
The power-on reset circuit disclosed in the document 3 has an enhancement-type PMOS 51 the source of which is connected to a power supply potential Vdd and has a voltage control circuit 52 connected between the drain of the PMOS 51 and the ground thereof, as shown in FIG. 26. The voltage control circuit 52 has a depression-type NMOS 52a the drain of which is connected to the source of the PMOS 51, and has an enhancement-type NMOS 52b the gate and drain of which are connected to the gate and source of the NMOS 52a. The source of the NMOS 52b is connected to the ground. The drain of an enhancement-type NMOS 54 and a pulse generation part 53 are connected to the output terminal of the voltage control circuit 52. The source of the enhancement-type NMOS 54 is grounded. The pulse generation part 53 has an enhancement-type PMOS 53a the source of which is connected to the power supply potential Vdd, a capacitor 53b connected between the PMOS 53a and the ground thereof and an inverter 53c the input terminal of which is connected to the connection point of the PMOS 53a and the capacitor 53b. The output side of the inverter 53c in the pulse generation part 53 is connected to the output terminal and the inverter 55. The output side of the inverter 55 is connected to the gate of the PMOS 51 and the gate of the NMOS 54.
Further in the power-on reset circuit disclosed in the document 3, when the off-leakage current is sent on the PMOS 53a in the pulse generation part 53 the charge of the capacitor 53b is started by the off-leakage current through the PMOS 53a and the PMOS 51 is forced to be turned off by inverting the outputs of the inverters 53c and 55 and PMOS 53a in the pulse generation part 53 is forced to be turned on, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the power supply voltage value at which the voltage control circuit 52 starts outputting the voltage difference from the voltage Vdd at which the PMOS 53a in the pulse generation part 53 is turned on. As a result, a one-shot pulse (power-on reset signal) cannot be accurately generated.
The power-on reset circuit disclosed in the document 4 has a power supply voltage sensing circuit 60, a capacitor charge time constant circuit 70 and an output circuit 75, as shown in FIG. 27. The power supply voltage sensing circuit 60 has a first transistor PMOS 61 the source of which is connected to the first power supply potential Vcc and which functions as an electric current path disconnecting means, and has PMOS 62 and PMOS 63 which form a rectifier functioning as a voltage sensing means and which are connected between the drain of the PMOS 61 and a second power supply potential, that is, a ground GND. The voltage difference between a potential Vcc and the ground GND shows the supplied power supply potential Vcc. The source of the PMOS 62 is connected to the drain of the PMOS 61. A first connection node N60 of the drain of the PMOS 61 and the source of the PMOS 62 is the output terminal of the power supply voltage sensing circuit 60. The capacitor charge time constant circuit 70 has a second transistor PMOS 71 the gate of which is connected to a node N60, the source of which is connected to the power supply potential Vcc and which functions as an electric current flowing path means, and has a third transistor PMOS 72 the gate of which is connected to the power supply potential Vcc and which functions as a discharging means. The drain of the PMOS 71 is connected to the source of the PMOS 72 and to one electrode of the capacitor 73. The drain of the PMOS 72 and the other electrode of the capacitor 73 are connected to the ground GND in common. The gate of the PMOS 72 is connected to the power supply potential Vcc. The connection point of the drain of the PMOS 71, the source of the PMOS 72 and the capacitor 73 is a second node N70, which is connected to the gate of the PMOS 61 as the output terminal of the capacitor charge time constant circuit 70 and to the input terminal of the inverter 75. The inverter 75 is driven by the power supply potential Vcc as the power supply voltage sensing circuit 60 and the capacitor charge time constant circuit 70, and an one-shot pulse is output from the output terminal of the inverter 75.
Further in the power-on reset circuit disclosed in the document 4, when the off-leakage current is sent on the PMOS 71 in the capacitor charge time constant circuit 70, the charge of the capacitor 73 is started by the off-leakage current through the PMOS 71, at the ramp-up period of the power supply voltage in the power application, before the power supply voltage reaches the power supply voltage value at which the power supply voltage sensing circuit 60 starts outputting the voltage difference from the voltage Vdd at which the PMOS 71 in the capacitor charge time constant circuit 70 is turned on. As a result, the one-shot pulse (power-on reset signal) cannot be accurately generated.
As described above, the conventional power-on reset circuit, in which the one-shot pulse is generated even when the ramp-up speed of the power supply voltage is slower than the time constant of the capacitor charge, has the circuit configuration that the supply of time constant current-charging to the capacitor is controlled by a MOS active element, and the countermeasure to the MOS element leakage current is not taken. Therefore, when the conventional power-on reset circuit is configured by using a minute MOS element in which the off-leakage current through the MOS (under high temperature) tends to increase with recent development of process-minuteness of the semiconductor integrated circuit, it is difficult to generate the one-shot pulse accurately.
To achieve the above object, in the first aspect of the present invention, there is provided a power-on reset circuit comprising: a first node to which a power supply voltage is supplied; a second node to which a reference voltage is supplied; a voltage supply circuit which has a first switch electrically connecting the first node with a fourth node in response to a voltage level of a third node, and a diode being connected to the second node and to the fourth node; a time constant circuit which has a second switch electrically connecting the first node with the third node in response to the voltage level of the fourth node, and a capacitor being connected to the second node and to the third node; and a third switch which electrically connects the second node with the third node in response to the voltage level of the fourth node.
In the second aspect of the present invention, there is provided a power-on reset circuit comprising a power supply voltage sensing circuit, a capacitance element charge time constant circuit, an off-leakage current capacitance element charge cutoff circuit and an output circuit. The power supply voltage sensing circuit comprises a voltage sensing means connected between a first power supply potential and a second power potential which show the power supply voltage by the potential difference to flow and form the electric current path when the power supply voltage reaches more than a specific threshold value and showing the sensed voltage on a first node, and an electric current path disconnecting means achieving on-off control based on the feedback voltage to disconnect the electric current path in the off-state. Further, the power supply voltage sensing circuit senses the power supply voltage application with the electric current path disconnecting means on-state.
The capacitance element charge time constant circuit comprises an electric current flowing path means connected between the first power supply potential and the second node and flowing path based on the sensed voltage, a capacitance element connected between the second node and the second power supply potential to charge based on the time constant through the electric current flowing path means, and a discharging means flowing path when the power supply voltage is less than the specific threshold voltage to discharge the capacitance element.
The off-leakage current capacitance element charge cutoff circuit comprises a charge cutoff means cutting off the charge to the capacitance element by the off-leakage current from the electric current flowing path means in the capacitance element charge time constant circuit.
The output circuit, the driving source of which is the power source voltage, judges the second-node voltage by a specific threshold value and outputs an one-shot pulse with logical-level in response to the judging result.
Further, there is provided a power-on reset circuit wherein the second node voltage is applied to the charge cutoff means in the power supply voltage sensing circuit as the feedback voltage, the charge to the capacitance element by the off-leakage current from the electric current flowing path means in the capacitance element charge time constant circuit is cut off by the charge cutoff means in the off-leakage current capacitance element charge cutoff circuit when the power supply voltage is less than the specific threshold voltage, and the charge to the capacitance element in the capacitance element charge time constant circuit starts when the power supply voltage becomes more than the specific threshold voltage.
Further, in the third aspect of the present invention, there is provided a power-on reset circuit comprising a power supply voltage sensing circuit, a capacitance element charge time constant circuit, an off-leakage current capacitance element charge cutoff circuit, an output circuit and an inverter element. The power supply voltage sensing circuit comprises a voltage sensing means connected between a first power supply potential and a second power potential which show the power supply voltage by the potential difference to flow and form the electric current path when the power supply voltage reaches more than a specific threshold value and showing the sensed voltage on a first node, and an electric current path disconnecting means achieving on-off control based on the feedback voltage to disconnect the electric current path in the off-state. Further, the power supply voltage sensing circuit senses the power supply voltage application with the electric current path disconnecting means on-state.
The capacitance element charge time constant circuit comprises an electric current flowing path means connected between the first power supply potential and the second node and flowing path based on the sensed voltage, a capacitance element connected between the second node and the second power supply potential to charge based on the time constant through the electric current flowing path means, a discharging means flowing path when the power supply voltage is less than the specific threshold voltage to discharge the capacitance element.
The off-leakage current capacitance element charge cutoff circuit has a charge cutoff means cutting off the charge to the capacitance element by the off-leakage current from the electric current flowing path means in the capacitance element charge time constant circuit.
The output circuit, the driving source of which is the power source voltage, judges the second-node voltage by a specific threshold value and outputs an one-shot pulse with logical-level in response to the judging result.
The inverter element outputs a one-shot pulse inversion signal to clamp the operation of the power supply voltage sensing circuit after the output of the one-shot pulse from the output circuit.
Further, there is provided a power-on reset circuit wherein the second node voltage is applied to the charge cutoff means as the feedback voltage, the charge to the capacitance element by the off-leakage current from the electric current flowing path means in the capacitance element charge time constant circuit is cut off by the charge cutoff means in the off-leakage current capacitance element charge cutoff circuit when the power supply voltage is less than the specific threshold voltage, and the charge to the capacitance element in the capacitance element charge time constant circuit starts when the power supply voltage becomes more than the specific threshold voltage.